/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_G8_PINMUX_REG $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 28 Feb 2023 09:48:19 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  G8_PINMUX_REG_REG_SD0_CLK  0x0
#define  G8_PINMUX_REG_REG_SD0_CMD  0x4
#define  G8_PINMUX_REG_REG_SD0_D0  0x8
#define  G8_PINMUX_REG_REG_SD0_D1  0xc
#define  G8_PINMUX_REG_REG_SD0_D2  0x10
#define  G8_PINMUX_REG_REG_SD0_D3  0x14
#define  G8_PINMUX_REG_REG_SD0_CLK_PU_EN   0x0
#define  G8_PINMUX_REG_REG_SD0_CLK_PU_EN_OFFSET 2
#define  G8_PINMUX_REG_REG_SD0_CLK_PU_EN_MASK   0x4
#define  G8_PINMUX_REG_REG_SD0_CLK_PU_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_CLK_PD_EN   0x0
#define  G8_PINMUX_REG_REG_SD0_CLK_PD_EN_OFFSET 3
#define  G8_PINMUX_REG_REG_SD0_CLK_PD_EN_MASK   0x8
#define  G8_PINMUX_REG_REG_SD0_CLK_PD_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_CLK_PIN_SEL_EN   0x0
#define  G8_PINMUX_REG_REG_SD0_CLK_PIN_SEL_EN_OFFSET 4
#define  G8_PINMUX_REG_REG_SD0_CLK_PIN_SEL_EN_MASK   0xf0
#define  G8_PINMUX_REG_REG_SD0_CLK_PIN_SEL_EN_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_CLK_DRI_SEL   0x0
#define  G8_PINMUX_REG_REG_SD0_CLK_DRI_SEL_OFFSET 8
#define  G8_PINMUX_REG_REG_SD0_CLK_DRI_SEL_MASK   0xf00
#define  G8_PINMUX_REG_REG_SD0_CLK_DRI_SEL_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_CLK_SCT_EN   0x0
#define  G8_PINMUX_REG_REG_SD0_CLK_SCT_EN_OFFSET 12
#define  G8_PINMUX_REG_REG_SD0_CLK_SCT_EN_MASK   0x1000
#define  G8_PINMUX_REG_REG_SD0_CLK_SCT_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_CLK_OEX_EN   0x0
#define  G8_PINMUX_REG_REG_SD0_CLK_OEX_EN_OFFSET 13
#define  G8_PINMUX_REG_REG_SD0_CLK_OEX_EN_MASK   0x2000
#define  G8_PINMUX_REG_REG_SD0_CLK_OEX_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_CMD_PU_EN   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_PU_EN_OFFSET 2
#define  G8_PINMUX_REG_REG_SD0_CMD_PU_EN_MASK   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_PU_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_CMD_PD_EN   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_PD_EN_OFFSET 3
#define  G8_PINMUX_REG_REG_SD0_CMD_PD_EN_MASK   0x8
#define  G8_PINMUX_REG_REG_SD0_CMD_PD_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_CMD_PIN_SEL_EN   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_PIN_SEL_EN_OFFSET 4
#define  G8_PINMUX_REG_REG_SD0_CMD_PIN_SEL_EN_MASK   0xf0
#define  G8_PINMUX_REG_REG_SD0_CMD_PIN_SEL_EN_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_DRI_SEL   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_DRI_SEL_OFFSET 8
#define  G8_PINMUX_REG_REG_SD0_CMD_DRI_SEL_MASK   0xf00
#define  G8_PINMUX_REG_REG_SD0_CMD_DRI_SEL_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_SCT_EN   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_SCT_EN_OFFSET 12
#define  G8_PINMUX_REG_REG_SD0_CMD_SCT_EN_MASK   0x1000
#define  G8_PINMUX_REG_REG_SD0_CMD_SCT_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_CMD_OEX_EN   0x4
#define  G8_PINMUX_REG_REG_SD0_CMD_OEX_EN_OFFSET 13
#define  G8_PINMUX_REG_REG_SD0_CMD_OEX_EN_MASK   0x2000
#define  G8_PINMUX_REG_REG_SD0_CMD_OEX_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D0_PU_EN   0x8
#define  G8_PINMUX_REG_REG_SD0_D0_PU_EN_OFFSET 2
#define  G8_PINMUX_REG_REG_SD0_D0_PU_EN_MASK   0x4
#define  G8_PINMUX_REG_REG_SD0_D0_PU_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D0_PD_EN   0x8
#define  G8_PINMUX_REG_REG_SD0_D0_PD_EN_OFFSET 3
#define  G8_PINMUX_REG_REG_SD0_D0_PD_EN_MASK   0x8
#define  G8_PINMUX_REG_REG_SD0_D0_PD_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D0_PIN_SEL_EN   0x8
#define  G8_PINMUX_REG_REG_SD0_D0_PIN_SEL_EN_OFFSET 4
#define  G8_PINMUX_REG_REG_SD0_D0_PIN_SEL_EN_MASK   0xf0
#define  G8_PINMUX_REG_REG_SD0_D0_PIN_SEL_EN_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_D0_DRI_SEL   0x8
#define  G8_PINMUX_REG_REG_SD0_D0_DRI_SEL_OFFSET 8
#define  G8_PINMUX_REG_REG_SD0_D0_DRI_SEL_MASK   0xf00
#define  G8_PINMUX_REG_REG_SD0_D0_DRI_SEL_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_D0_SCT_EN   0x8
#define  G8_PINMUX_REG_REG_SD0_D0_SCT_EN_OFFSET 12
#define  G8_PINMUX_REG_REG_SD0_D0_SCT_EN_MASK   0x1000
#define  G8_PINMUX_REG_REG_SD0_D0_SCT_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D0_OEX_EN   0x8
#define  G8_PINMUX_REG_REG_SD0_D0_OEX_EN_OFFSET 13
#define  G8_PINMUX_REG_REG_SD0_D0_OEX_EN_MASK   0x2000
#define  G8_PINMUX_REG_REG_SD0_D0_OEX_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D1_PU_EN   0xc
#define  G8_PINMUX_REG_REG_SD0_D1_PU_EN_OFFSET 2
#define  G8_PINMUX_REG_REG_SD0_D1_PU_EN_MASK   0x4
#define  G8_PINMUX_REG_REG_SD0_D1_PU_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D1_PD_EN   0xc
#define  G8_PINMUX_REG_REG_SD0_D1_PD_EN_OFFSET 3
#define  G8_PINMUX_REG_REG_SD0_D1_PD_EN_MASK   0x8
#define  G8_PINMUX_REG_REG_SD0_D1_PD_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D1_PIN_SEL_EN   0xc
#define  G8_PINMUX_REG_REG_SD0_D1_PIN_SEL_EN_OFFSET 4
#define  G8_PINMUX_REG_REG_SD0_D1_PIN_SEL_EN_MASK   0xf0
#define  G8_PINMUX_REG_REG_SD0_D1_PIN_SEL_EN_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_D1_DRI_SEL   0xc
#define  G8_PINMUX_REG_REG_SD0_D1_DRI_SEL_OFFSET 8
#define  G8_PINMUX_REG_REG_SD0_D1_DRI_SEL_MASK   0xf00
#define  G8_PINMUX_REG_REG_SD0_D1_DRI_SEL_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_D1_SCT_EN   0xc
#define  G8_PINMUX_REG_REG_SD0_D1_SCT_EN_OFFSET 12
#define  G8_PINMUX_REG_REG_SD0_D1_SCT_EN_MASK   0x1000
#define  G8_PINMUX_REG_REG_SD0_D1_SCT_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D1_OEX_EN   0xc
#define  G8_PINMUX_REG_REG_SD0_D1_OEX_EN_OFFSET 13
#define  G8_PINMUX_REG_REG_SD0_D1_OEX_EN_MASK   0x2000
#define  G8_PINMUX_REG_REG_SD0_D1_OEX_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D2_PU_EN   0x10
#define  G8_PINMUX_REG_REG_SD0_D2_PU_EN_OFFSET 2
#define  G8_PINMUX_REG_REG_SD0_D2_PU_EN_MASK   0x4
#define  G8_PINMUX_REG_REG_SD0_D2_PU_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D2_PD_EN   0x10
#define  G8_PINMUX_REG_REG_SD0_D2_PD_EN_OFFSET 3
#define  G8_PINMUX_REG_REG_SD0_D2_PD_EN_MASK   0x8
#define  G8_PINMUX_REG_REG_SD0_D2_PD_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D2_PIN_SEL_EN   0x10
#define  G8_PINMUX_REG_REG_SD0_D2_PIN_SEL_EN_OFFSET 4
#define  G8_PINMUX_REG_REG_SD0_D2_PIN_SEL_EN_MASK   0xf0
#define  G8_PINMUX_REG_REG_SD0_D2_PIN_SEL_EN_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_D2_DRI_SEL   0x10
#define  G8_PINMUX_REG_REG_SD0_D2_DRI_SEL_OFFSET 8
#define  G8_PINMUX_REG_REG_SD0_D2_DRI_SEL_MASK   0xf00
#define  G8_PINMUX_REG_REG_SD0_D2_DRI_SEL_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_D2_SCT_EN   0x10
#define  G8_PINMUX_REG_REG_SD0_D2_SCT_EN_OFFSET 12
#define  G8_PINMUX_REG_REG_SD0_D2_SCT_EN_MASK   0x1000
#define  G8_PINMUX_REG_REG_SD0_D2_SCT_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D2_OEX_EN   0x10
#define  G8_PINMUX_REG_REG_SD0_D2_OEX_EN_OFFSET 13
#define  G8_PINMUX_REG_REG_SD0_D2_OEX_EN_MASK   0x2000
#define  G8_PINMUX_REG_REG_SD0_D2_OEX_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D3_PU_EN   0x14
#define  G8_PINMUX_REG_REG_SD0_D3_PU_EN_OFFSET 2
#define  G8_PINMUX_REG_REG_SD0_D3_PU_EN_MASK   0x4
#define  G8_PINMUX_REG_REG_SD0_D3_PU_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D3_PD_EN   0x14
#define  G8_PINMUX_REG_REG_SD0_D3_PD_EN_OFFSET 3
#define  G8_PINMUX_REG_REG_SD0_D3_PD_EN_MASK   0x8
#define  G8_PINMUX_REG_REG_SD0_D3_PD_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D3_PIN_SEL_EN   0x14
#define  G8_PINMUX_REG_REG_SD0_D3_PIN_SEL_EN_OFFSET 4
#define  G8_PINMUX_REG_REG_SD0_D3_PIN_SEL_EN_MASK   0xf0
#define  G8_PINMUX_REG_REG_SD0_D3_PIN_SEL_EN_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_D3_DRI_SEL   0x14
#define  G8_PINMUX_REG_REG_SD0_D3_DRI_SEL_OFFSET 8
#define  G8_PINMUX_REG_REG_SD0_D3_DRI_SEL_MASK   0xf00
#define  G8_PINMUX_REG_REG_SD0_D3_DRI_SEL_BITS   0x4
#define  G8_PINMUX_REG_REG_SD0_D3_SCT_EN   0x14
#define  G8_PINMUX_REG_REG_SD0_D3_SCT_EN_OFFSET 12
#define  G8_PINMUX_REG_REG_SD0_D3_SCT_EN_MASK   0x1000
#define  G8_PINMUX_REG_REG_SD0_D3_SCT_EN_BITS   0x1
#define  G8_PINMUX_REG_REG_SD0_D3_OEX_EN   0x14
#define  G8_PINMUX_REG_REG_SD0_D3_OEX_EN_OFFSET 13
#define  G8_PINMUX_REG_REG_SD0_D3_OEX_EN_MASK   0x2000
#define  G8_PINMUX_REG_REG_SD0_D3_OEX_EN_BITS   0x1
